1. Field of the Invention
The present invention generally relates to the field of phase lock loop frequency synthesizers and multipliers, and specifically to a hybrid phase lock loop that includes a digital phase lock loop and an analog phase lock loop.
2. Description of the Related Art
Generally, communication systems utilize various forms of phase lock loop (PLL) circuits to synchronize one or more output signals, e.g., carrier signals, to a reference signal. One conventional analog PLL includes a stable low frequency reference oscillator, e.g., a voltage controlled crystal oscillator (VCXO), coupled to a harmonic generator. A signal output of the harmonic generator provides a reference signal to an analog phase detector. A filtered version of an error signal from the analog phase detector is input to a voltage controlled oscillator (VCO). The oscillator generates an output carrier signal at a desired frequency. The phase detector adjusts (e.g., tunes) the oscillator to synchronize the frequency and phase to the error signal. Unfortunately, the analog PLL adjusts only over a narrow frequency range (i.e., tuning range) due to the limited capture range of the analog phase detector. The analog PLL can phase lock to any harmonic frequency of the reference signal that falls within the tuning range.
Conventional digital PLLs overcome many of the disadvantages of the analog PLL, such as the harmonic lock problem. A digital PLL generally includes a reference oscillator that provides a reference signal to a first digital frequency divider. An output of the first digital frequency divider is coupled to a digital frequency/phase detector. An output of the digital frequency/phase detector is coupled through a loop filter to an output oscillator. A sample of the output carrier signal generated by the output oscillator is coupled to a second digital frequency divider. A signal output of the second digital frequency divider is coupled as a feedback signal to the frequency/phase detector for comparison with the divided reference signal. The output carrier signal frequency is determined by the frequency of the reference signal multiplied by the ratio of the second digital divider to the first digital divider. Due to the wider capture range of the digital frequency/phase detector, the digital PLL provides tuning over a wide range of output carrier signal frequencies. Unfortunately, the digital implementation also encumbers the digital PLL with greater phase noise relative to the analog PLL.
Hybrid PLLs have been developed to capitalize on the benefits and avoid limitations of both the analog PLL and the digital PLL, as shown, for example, in U.S. Pat. No. 6,028,460. FIG. 1 illustrates a prior art hybrid PLL frequency synthesizer 100. Generally, such hybrid PLL frequency synthesizer 100 incorporates a hybrid PLL. The hybrid PLL includes a digital PLL 105 and an analog PLL 103. The digital PLL 105 and the analog PLL 103 are configured to individually acquire and phase lock an output carrier signal 121 from an output oscillator 120 to a reference signal 102 provided by a reference oscillator 101. Generally, during a frequency acquisition mode, the digital PLL 105 is used to acquire phase lock. Once the digital PLL 105 is phase locked, a switch 115 switches control of the hybrid PLL from the digital PLL 105 to the analog PLL 103. The analog PLL 103 then phase locks the output carrier signal 121 to a harmonic of the reference signal 102. The analog PLL 103 generally provides superior phase noise performance relative to the digital PLL 105.
The digital PLL 105 includes a digital divider 111, a digital phase detector 113, and a charge pump 114. The digital divider 111 digitally divides a sample of the output carrier signal 121 to the same frequency as the reference signal 102. The digitally divided signal is coupled to the digital phase detector 113 for frequency/phase comparison to the reference signal 102. The digital phase detector 113 provides phase control signals to the charge pump 114. The charge pump 114 provides a digital PLL control signal to a switch 115. When the digital PLL 105 is switched in control of the hybrid PLL, the switch 115 provides the digital control signal to a loop filter 117. The loop filter 117 filters the digital PLL control signal before being coupled to the output oscillator 120.
The analog PLL 103 includes a harmonic multiplier 107 to multiply the reference signal 102 to the same frequency of the output carrier signal 121, or to a down converted version thereof. An analog phase detector 109 generates an analog control signal indicative of a phase comparison between the multiplied reference signal and a sample of output carrier signal 121. When the analog PLL 103 is switched in control of the hybrid PLL, the switch 115 provides the analog PLL control signal from the analog phase detector 109 to the loop filter 115. The loop filter 115 filters the analog PLL control signal before being coupled to the output oscillator 120.
Generally, the hybrid PLL requires the switch 115 to alternate complete PLL control between the analog PLL 103 and the digital PLL 105 depending on whether the frequency synthesizer 100 is in an acquisition mode or is in a steady state phase locked mode. Therefore, depending upon the state of switch 115, the hybrid PLL is controlled only by the analog PLL 103 or the digital PLL 105.
Once the analog PLL 103 is phase locked, the digital PLL 105 monitors the phase and frequency lock after switching control of the hybrid PLL to the analog PLL 103. If large frequency and/or phase perturbations of the analog PLL 103 are sensed, then switch 115 switches control of the hybrid PLL completely from the analog PLL 103 to the digital PLL 105. Under such conditions, the digital PLL 105 takes complete control of the hybrid PLL to reacquire phase lock. Once phase lock is reacquired, the switch 115 switches control of the hybrid PLL completely from the digital PLL 105 to the analog PLL 103.
Generally, the digital phase detector 113 generates digital signals, e.g., pulse shaped waveforms, having pulse widths associated with the time difference, i.e., skew, between such waveforms. For example, the digital signals are coupled to the charge pump 114. Based on the pulse widths, the charge pump 114 provides the digital PLL control signal to the output oscillator 120 via the loop filter 115.
Generally, the digital phase detector 113 provides the digital control signals to the charge pump 113 in the form of digital pump up or pump down signals depending on whether the reference signal 102 is leading or lagging the output signal 121 in phase. For example, the digital phase detector 113 provides the digital pump up signals when the reference signal 102 leads the output signal 121 in phase. Conversely, the digital phase detector 113 provides the digital pump down signals when the reference signal 102 lags the output signal 121 in phase.
Unfortunately, the phase detector 113 and the charge pump 114 have response limitations, i.e., bandwidth constraints. The narrower the phase difference between the reference signal 102 and the output signal 121, the narrower the pulse widths of the digital pump up signals and digital pump down signals. Under conditions when the phase of the reference signal 102 and the output signal 121 is within a predetermined range of phase variance, the pump up signals and the digital pump down signals generally become too narrow to cause a response by the charge pump 114. Accordingly, under such conditions, the charge pump 114 transitions to a non-responsive state which drops the gain of the digital PLL 105 to virtually zero.
Generally, under conditions when the charge pump 114 provides such a zero or null output to the output oscillator 120, the digital PLL 105 is considered to be in a dead band state. The dead band state corresponds to a zone of operation in which the loop gain of the digital PLL 105 is essentially zero. The loss of digital PLL 105 gain within the dead band may be referred to as the dead band effect.
Depending on the digital implementation, the dead band effect may be a significant detriment. Typically, digital PLL designers go to great lengths to avoid the dead band effect because the dead band effect leads to greater phase noise. The phase noise is detrimentally affected especially close in frequency to the output signal 121 (i.e., at small offset frequencies from the output signal 121), for which the digital PLL 105 has little control due to minimal loop gain.
Solutions for overcoming the dead band effect include narrowing the dead band. However, narrowing the dead band typically causes an increase in circuitry complexity and cost, e.g., a more responsive charge pump 114. Other solutions include using the pulse width differences between the digital pump up signals and the digital pump down signals to adjust the charge pump 114, or providing a slight phase/frequency offset to slightly unbalance the digital PLL 105 away from the dead band. The phase/frequency offset provides some loop gain, thereby allowing the digital PLL 105 to exert some control over the hybrid PLL 100. Unfortunately, providing the phase/frequency offset is difficult to implement, requires specialized circuitry, drifts over temperature, and generally exacerbates phase noise and spurious signal issues.